[STATEMENT]
lemma mem_read_mod_state: "fst (memory_read asi addr s) =
fst (memory_read asi addr
(s\<lparr>cpu_reg := new_cpu_reg,
   user_reg := new_user_reg,
   dwrite := new_dwrite,
   state_var := new_state_var,
   traps := new_traps,
   undef := new_undef\<rparr>))"
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. fst (memory_read asi addr s) = fst (memory_read asi addr (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))
[PROOF STEP]
apply (simp add: memory_read_def)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 1")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 1 \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. uint asi \<noteq> 1 \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 1 \<Longrightarrow> (load_word_mem s addr 10 = None \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10 = None \<longrightarrow> (load_word_mem s addr 8 = None \<longrightarrow> (\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> None = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8) \<and> ((\<exists>y. load_word_mem s addr 8 = Some y) \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 8 = None) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8))) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10 = Some y) \<longrightarrow> (load_word_mem s addr 8 = None \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> None = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> None = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8)) \<and> ((\<exists>y. load_word_mem s addr 8 = Some y) \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8)))) \<and> ((\<exists>y. load_word_mem s addr 10 = Some y) \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10 = None \<longrightarrow> (load_word_mem s addr 8 = None \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 10 = None) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 10 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8)) \<and> ((\<exists>y. load_word_mem s addr 8 = Some y) \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 8 = None) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8))) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10 = Some y) \<longrightarrow> (load_word_mem s addr 8 = None \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 10 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 10 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8)) \<and> ((\<exists>y. load_word_mem s addr 8 = Some y) \<longrightarrow> (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = None \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 10) \<and> ((\<exists>y. load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8 = Some y) \<longrightarrow> load_word_mem s addr 8 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr 8))))
 2. uint asi \<noteq> 1 \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (metis load_word_mem_mod_state option.distinct(1))
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. uint asi \<noteq> 1 \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 2")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi = 2\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 2 \<Longrightarrow> (uint addr = 12 \<longrightarrow> sys_reg_val DCCR s = sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> sys_reg_val ICCR s = sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) \<and> (uint addr \<noteq> 8 \<longrightarrow> uint addr = 0 \<longrightarrow> sys_reg_val CCR s = sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: sys_reg_val_def)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi \<in> {8,9}")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<in> {8, 9}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi = 8 \<or> uint asi = 9\<rbrakk> \<Longrightarrow> (sys_reg s CCR AND 1 \<noteq> 0 \<longrightarrow> fst (case load_word_mem s addr asi of None \<Rightarrow> (None, s) | Some w \<Rightarrow> (Some w, add_instr_cache s addr w 15)) = fst (case load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi of None \<Rightarrow> (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) | Some w \<Rightarrow> (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) \<and> (sys_reg s CCR AND 1 = 0 \<longrightarrow> load_word_mem s addr asi = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi)
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: load_word_mem3_mod_state)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi = 8 \<or> uint asi = 9\<rbrakk> \<Longrightarrow> sys_reg s CCR AND 1 = 0 \<longrightarrow> load_word_mem s addr asi = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: load_word_mem_mod_state)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi \<in> {10,11}")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<in> {10, 11}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<noteq> 8 \<and> uint asi \<noteq> 9; uint asi = 10 \<or> uint asi = 11\<rbrakk> \<Longrightarrow> (sys_reg s CCR AND 1 \<noteq> 0 \<longrightarrow> fst (case load_word_mem s addr asi of None \<Rightarrow> (None, s) | Some w \<Rightarrow> (Some w, add_data_cache s addr w 15)) = fst (case load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi of None \<Rightarrow> (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) | Some w \<Rightarrow> (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) \<and> (sys_reg s CCR AND 1 = 0 \<longrightarrow> load_word_mem s addr asi = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi)
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: load_word_mem2_mod_state)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<noteq> 8 \<and> uint asi \<noteq> 9; uint asi = 10 \<or> uint asi = 11\<rbrakk> \<Longrightarrow> sys_reg s CCR AND 1 = 0 \<longrightarrow> load_word_mem s addr asi = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: load_word_mem_mod_state)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 13")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi = 13\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 13 \<Longrightarrow> fst (case read_instr_cache s addr of None \<Rightarrow> (None, s) | Some w \<Rightarrow> (Some w, s)) = fst (case read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr of None \<Rightarrow> (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) | Some w \<Rightarrow> (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: read_icache2_mod_state)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 15")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi = 15\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 15 \<Longrightarrow> fst (case read_data_cache s addr of None \<Rightarrow> (None, s) | Some w \<Rightarrow> (Some w, s)) = fst (case read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr of None \<Rightarrow> (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) | Some w \<Rightarrow> (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: read_dcache2_mod_state)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 25")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi = 25\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (case_tac "uint asi = 28")
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25; uint asi = 28\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25; uint asi \<noteq> 28\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: Let_def)
[PROOF STATE]
proof (prove)
goal (2 subgoals):
 1. uint asi = 28 \<Longrightarrow> mem_val_w32 asi (ucast addr) s = mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)
 2. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25; uint asi \<noteq> 28\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
apply (simp add: mem_val_w32_mod_state)
[PROOF STATE]
proof (prove)
goal (1 subgoal):
 1. \<lbrakk>uint asi \<noteq> 1; uint asi \<noteq> 2; uint asi \<notin> {8, 9}; uint asi \<notin> {10, 11}; uint asi \<noteq> 13; uint asi \<noteq> 15; uint asi \<noteq> 25; uint asi \<noteq> 28\<rbrakk> \<Longrightarrow> (uint addr = 12 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val DCCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val DCCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 12 \<longrightarrow> (uint addr = 8 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val ICCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val ICCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 8 \<longrightarrow> (uint addr = 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (Some (sys_reg_val CCR s), s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (Some (sys_reg_val CCR (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) \<and> (uint addr \<noteq> 0 \<longrightarrow> fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem s addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem s addr (word_of_int 10) in if r2 = None then (None, s) else (r2, s) else (r1, s) else if asi_int = 2 then (None, s) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_instr_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg s CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem s addr asi) (case_option (None, s) (\<lambda>w. (Some w, add_data_cache s addr w 15))) else (load_word_mem s addr asi, s) else if asi_int = 13 then Let (read_instr_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int = 15 then Let (read_data_cache s addr) (case_option (None, s) (\<lambda>w. (Some w, s))) else if asi_int \<in> {16, 17} then (None, s) else if asi_int \<in> {20, 21} then (None, s) else if asi_int = 24 then (None, s) else if asi_int = 25 then (mmu_reg_val (mmu s) addr, s) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) s, s) else if asi_int = 29 then (None, s) else (None, s)) = fst (let asi_int = uint asi in if asi_int = 1 then let r1 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 8) in if r1 = None then let r2 = load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr (word_of_int 10) in if r2 = None then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r2, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (r1, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 2 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {8, 9} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {10, 11} then let ccr_val = sys_reg (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) CCR in if ccr_val AND 1 \<noteq> 0 then Let (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr w 15))) else (load_word_mem (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr asi, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 13 then Let (read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int = 15 then Let (read_data_cache (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) addr) (case_option (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) (\<lambda>w. (Some w, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>))) else if asi_int \<in> {16, 17} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int \<in> {20, 21} then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 24 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 25 then (mmu_reg_val (mmu (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)) addr, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 28 then (mem_val_w32 asi (ucast addr) (s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>), s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else if asi_int = 29 then (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>) else (None, s\<lparr>cpu_reg := new_cpu_reg, user_reg := new_user_reg, dwrite := new_dwrite, state_var := new_state_var, traps := new_traps, undef := new_undef\<rparr>)))))
[PROOF STEP]
by (simp add: Let_def)